Aakriti Barat

Electrical Engineer

Ohio University

Biography

Hi! I’m Aakriti Barat. I’m working on my PhD in Electrical Engineering advised by Dr Savas Kaya at Ohio University. My research currently lies in hardware design from a cybersecurity perspective. Aside from my research, I keep myself busy by taking on new courses and projects.

Interests

Cybersecurity
Hardware Design
Embedded Systems
Data Analysis

Education

PhD in Electrical & Computer Engineering, 2024
Ohio University
M.S in Electrical & Computer Engineering, 2017
The Ohio State University
B.E in Electronics & Communication Engineering, 2014
Lakshmi Narain College of Technology

Skills

Python

VHDL

MATLAB

Mentor Graphics

Intel Quartus

Work & Research Experience

Research Assistant

Ohio University

May 2020 – Present Athens, OH

Assisted in organizing summer workshops in cybersecurity for high school teachers and K-12 students
Lab intructor for new Hardware Security course developed for upcoming Bachelors/Masters course in Cybersecurity
Teaching Assistant for Digital Circuits course that uses FPGA and VHDL toolsets

Sr Electrical Hardware Design Engineer

Vertiv

Dec 2017 – Mar 2020 Columbus, OH

Test equipment hardware and software integration
Testing and troubleshooting of prototypes and field returns
Analog & digital design
Design documentation - schematics , assembly and fabrication diagrams

Hardware Design Engineer

Thermo Fisher Scientific

Jun 2017 – Dec 2017 Cleveland, OH

PCBA testing
Test experimentation development
Multi-department collaboration
Quick promotion to managerial responsibilities
Design documentation specification and component engineering

Graduate Student

The Ohio State University

Jan 2017 – Feb 2017 Columbus, OH

Multiresolution analysis of injection locking in PLL using TopSpice
Study of fourier transforms on PLL outputs using MATLAB

Research Associate

IITM

Aug 2014 – Jul 2015 Chennai, IN

Designed thermal camera with lenslet array to capture night vision images
Algorithm development in VHDL for image processing on FPGA using Lattice Diamond